Production method of lll nitride compound semiconductor substrate and semiconductor device

ABSTRACT

A GaN layer  31  is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base  1.  Subsequently, a GaN layer  32  is lateral-epitaxially grown with the top surfaces of the mesas and sidewalls of the trenches serving as nuclei, to thereby fill upper portions of the trenches (depressions of the substrate base  1 ), and then epitaxial growth is effected in the vertical direction. In this case, propagation of threading dislocations contained in the GaN layer  31  can be prevented in the upper portion of the GaN layer  32  that is formed through lateral epitaxial growth. Thereafter, the remaining GaN layer  31  is removed through etching, together with the GaN layer  32  formed atop the GaN layer  31,  and subsequently, a GaN layer  33  is lateral-epitaxially grown with the top surfaces of mesas and sidewalls of trenches serving as nuclei, the mesas and trenches being formed of the remaining GaN layer  32,  thereby producing a GaN substrate  30  in which threading dislocations are considerably suppressed. When the area of a portion of the GaN layer  31  at which the GaN substrate  30  is in contact with the substrate base  1  is reduced, separation of the GaN substrate  30  from the substrate base  1  is readily attained.

TECHNICAL FIELD

[0001] The present invention relates to a method for fabricating GroupIII nitride compound semiconductor substrates. More particularly, thepresent invention relates to a method for fabricating Group III nitridecompound semiconductor substrates employing epitaxial lateral overgrowth(ELO). Like the case of semiconductor substrates produced by methodsother than the method of the present invention, the Group III nitridecompound semiconductor substrate produced by the method of the presentinvention is useful for forming a semiconductor device. The Group IIInitride compound semiconductors are generally represented byAl_(x)Ga_(y)In_(1−x−y)N (wherein 0≦x≦1, 0≦y≦1, and 0≦x+y≦1), andexamples thereof include binary semiconductors such as AlN, GaN, andInN; ternary semiconductors such as Al_(x)Ga_(1−x)N, Al_(x)In_(1−x)N,and Ga_(x)In_(1−x)N (wherein 0<x<1); and quaternary semiconductors suchas Al_(x)Ga_(y)In_(1−x−y)N (wherein 0<x<1, 0<y<1, and 0<x+y<1). In thepresent specification, unless otherwise specified, “Group III nitridecompound semiconductors” comprise Group III nitride compoundsemiconductors which are doped with an impurity so as to get p-type orn-type conductivity.

BACKGROUND ART

[0002] Group III nitride compound semiconductor are direct-transitiontype of semiconductors exhibiting a wide range of emission spectra fromUV to red light when used in a device such as a light-emitting device,for example, light-emitting diodes (LEDs) and laser diodes (LDs). Inaddition, due to their wide band gaps, devices employing theaforementioned semiconductors are expected to exhibit reliableoperational characteristics at high temperature as compared with thoseemploying semiconductors of other types, and thus application thereof totransistors such as FETs has been energetically studied. Moreover,because Group III nitride compound semiconductors contain no arsenic(As) as a predominant element, application of Group III nitride compoundsemiconductors to various semiconductor elements has been expected fromthe environmental aspect. Generally, these Group III nitride compoundsemiconductors are formed on a sapphire substrate.

DISCLOSURE OF THE INVENTION

[0003] However, when a Group III nitride compound semiconductor isformed on a sapphire substrate, misfit-induced dislocations occur due todifference between the lattice constant of sapphire and that of thesemiconductor, resulting in poor device characteristics. Misfit-induceddislocations are threading dislocations which penetrate semiconductorlayers in a longitudinal direction (i.e., in a direction vertical to thesurface of the substrate), and Group III nitride compound semiconductorsare accompanied by the problem that dislocations in amounts ofapproximately 10⁹ cm⁻² propagate therethrough. The aforementioneddislocations propagate through layers formed from Group III nitridecompound semiconductors of different compositions, until they reach theuppermost layer. When such a semiconductor is incorporated in, forexample, a light-emitting device, the device poses problems ofunsatisfactory device characteristics in terms of threshold current ofan LD, a life time of an LED or LD, etc. On the other hand, when a GroupIII nitride compound semiconductor is incorporated in any of other typesof semiconductor devices, because electrons are scattered due to defectsin the Group III nitride compound semiconductor, the semiconductorelement comes to have low mobility. These problems are not solved evenwhen another type of substrate is employed.

[0004] The aforementioned dislocations will next be described withreference to a schematic representation shown in FIG. 9. FIG. 9 shows asubstrate 91, a buffer layer 92 formed thereon, and a Group III nitridecompound semiconductor layer 93 further formed thereon. Conventionally,the substrate 91 is formed of sapphire or a similar substance and thebuffer layer 92 is formed of aluminum nitride (AlN) or a similarsubstance. The buffer layer 92 formed of aluminum nitride (AlN) isprovided so as to relax misfit between the sapphire substrate 91 and theGroup III nitride compound semiconductor layer 93. However, generationof dislocations is not reduced to zero. Threading dislocations 901propagate upward (in a vertical direction with respect to the substratesurface) from dislocation initiating points 900, penetrating the bufferlayer 92 and the Group III nitride compound semiconductor layer 93. Whena semiconductor device is fabricated by laminating various types ofGroup III nitride compound semiconductors of interest on the Group IIInitride compound semiconductor layer 93, threading dislocations furtherpropagate upward, through the semiconductor device, from dislocationarrival points 902 on the surface of the Group III nitride compoundsemiconductor layer 93. Thus, according to conventional techniques,problematic propagation of dislocations cannot be prevented duringformation of Group III nitride compound semiconductor layers.

[0005] There have been proposed techniques in which a thick Group IIInitride compound semiconductor layer is formed on a substrate baseformed of a compound different from a Group III nitride compound, andsubsequently the substrate base is removed, to thereby produce a GroupIII nitride compound semiconductor substrate. Such techniques include atechnique called ELO or Pendeo ELO. However, the aforementionedtechniques have not been put into practice, since difficulty isencountered in removing a Group III nitride compound semiconductorsubstrate from the substrate base.

[0006] The present invention has been accomplished in an attempt tosolve the aforementioned problems, and an object of the presentinvention is to provide a convenient method for fabricating a Group IIInitride compound semiconductor substrate with suppressed generation ofthreading dislocations. Another object of the present invention is toprovide a semiconductor device including the Group III nitride compoundsemiconductor substrate with suppressed generation of threadingdislocations.

[0007] In order to solve the aforementioned problems, the inventiondrawn to a first feature provides a method for fabricating a Group IIInitride compound semiconductor substrate through epitaxial growth of aGroup III nitride compound semiconductor layer on a substrate base,followed by removal of the substrate base, which method comprises a stepof forming an underlying layer on a substrate base, the underlying layercomprising at least one Group III nitride compound semiconductor layer,and the uppermost layer of the underlying layer being a first Group IIInitride compound semiconductor layer; a first trench/mesa formation stepin which at least a portion of the underlying layer and at least aportion of the surface of the substrate base are removed through etchingso as to form an island-like structure having, for example, a dot,stripe, or grid shape, thereby providing a trench/mesa structureincluding mesas formed on the underlying layer and trenches whosebottoms sink into the surface of the substrate base; a first lateralepitaxial growth step in which a second Group III nitride compoundsemiconductor layer is epitaxially grown, vertically and laterally, withtop surfaces of the mesas and sidewalls of the trenches serving asnuclei for crystal growth, i.e., seeds for crystal growth, the mesas andtrenches being formed by etching of the first Group III nitride compoundsemiconductor layer so as to form an island-like structure having, forexample, a dot, stripe, or grid shape, thereby filling upper portions ofthe trenches and covering the mesas; a second trench/mesa formation stepin which the entire underlying layer that has not undergone etching inthe first trench/mesa formation step, excepting a portion of theunderlying layer, is removed by etching, together with the second GroupIII nitride compound semiconductor layer formed on the underlying layer,and at least a portion of the surface of the substrate base, so as toprovide a trench/mesa structure including mesas formed on the remainingsecond Group III nitride compound semiconductor layer and trenches whosebottoms sink into the surface of the substrate base; a second lateralepitaxial growth step in which a third Group III nitride compoundsemiconductor layer is epitaxially grown, vertically and laterally, withtop surfaces of the mesas and sidewalls of the trenches serving asnuclei for crystal growth, i.e., seeds for crystal growth, the mesas andtrenches being formed through etching of the second Group III nitridecompound semiconductor layer, thereby filling upper portions of thetrenches and covering the mesas; and a step of removing the substratebase and the underlying layer which has not been removed in the secondtrench/mesa formation step, to thereby produce a substrate comprisingthe second and third Group III nitride compound semiconductor layers. Inthe present specification, the term “underlying layer” is used tocollectively comprise a Group III nitride compound semiconductor singlelayer and a multi-lamellar layer containing at least one Group IIInitride compound semiconductor layer. The expression “island-likestructure” conceptually refers to the pattern of the upper portions ofthe mesas formed through etching, and does not necessarily refer toregions separated from one another. Thus, the upper portions of themesas may be continuously connected to one another over a considerablywide area, and such a structure may be obtained by forming the entiretyof a wafer into stripes or grids. The sidewall/sidewalls of the trenchrefer not only to planes that are vertical to the substrate plane andthe surface of a Group III nitride compound semiconductor layer, butalso to oblique planes. The trench may have a V-shaped cross section;i.e., the trench may have no bottom surface. The expression “fillingupper portions of the trench” does not necessarily refer to the casewhere the upper portions are completely filled so as to provide nospace, and a space may be provided. Examples of such a space include aspace generated through incomplete growth of a Group III nitridecompound semiconductor layer as a result of insufficient feeding of araw or source material to epitaxial growth fronts starting from thesidewalls of the trench; and a gap between the substrate plane and aGroup III nitride compound semiconductor layer. Unless otherwisespecified, these definitions are equally applied to the below-describedfeatures.

[0008] The invention drawn to a second feature provides a method forfabricating a Group III nitride compound semiconductor substratecomprising epitaxial growth of a Group III nitride compoundsemiconductor layer on a substrate base, and removal of the substratebase, which method comprises a step of forming an underlying layer on asubstrate base, the underlying layer comprising at least one Group IIInitride compound semiconductor layer, and the uppermost layer of theunderlying layer being a first Group III nitride compound semiconductorlayer; a first trench/mesa formation step in which the underlying layeris etched so as to form an island-like structure having, for example, adot, stripe, or grid shape, thereby providing a trench/mesa structure,such that the substrate base is exposed so as to provide the bottoms oftrenches; a first mask formation step in which first masks are formed atthe bottoms of the trenches formed in the first trench/mesa formationstep, such that the upper surfaces of the first masks are positionedbelow the top surface of the uppermost layer of the underlying layer; afirst lateral epitaxial growth step in which a second Group III nitridecompound semiconductor layer is epitaxially grown, vertically andlaterally, with top surfaces of mesas and sidewalls of the trenchesserving as nuclei for crystal growth, i.e., seeds for crystal growth,the mesas and trenches being formed by etching of the first Group IIInitride compound semiconductor layer so as to form an island-likestructure having, for example, a dot, stripe, or grid shape, therebyfilling spaces above the first masks and covering the mesas; a secondtrench/mesa formation step in which substantially the entire underlyinglayer that has not undergone etching in the first trench/mesa formationstep is removed through etching, together with the second Group IIInitride compound semiconductor layer formed on the underlying layer, soas to provide a trench/mesa structure including mesas formed on theremaining second Group III nitride compound semiconductor layer andtrenches such that the substrate base is exposed so as to provide thebottoms of the trenches; a second mask formation step in which secondmasks are formed at the bottoms of the trenches formed in the secondtrench/mesa formation step, such that the upper surfaces of the secondmasks are positioned below the top surface of the second Group IIInitride compound semiconductor layer; a second lateral epitaxial growthstep in which a third Group III nitride compound semiconductor layer isepitaxially grown, vertically and laterally, with top surfaces of themesas and sidewalls of the trenches serving as nuclei for crystalgrowth, i.e., seeds for crystal growth, the mesas and trenches beingformed by etching of the second Group III nitride compound semiconductorlayer, thereby filling spaces above the second masks and covering themesas; a step of removing the first and second masks by wet etching; anda step of removing the substrate base, to thereby produce a substratecomprising the second and third Group III nitride compound semiconductorlayers.

[0009] The invention drawn to a third feature provides a method forfabricating a Group III nitride compound semiconductor substrate asrecited in connection with the second feature, wherein the masks areformed of a substance capable of impeding epitaxial growth of a GroupIII nitride compound semiconductor layer on the masks.

[0010] The invention drawn to a fourth feature provides a method forfabricating a Group III nitride compound semiconductor substrate asrecited in connection with any one of the first through third features,wherein virtually all the sidewalls of the trenches formed in the firstand second trench/mesa formation steps are a {11-20} plane.

[0011] The invention drawn to a fifth feature provides a method forfabricating a Group III nitride compound semiconductor substrate asrecited in connection with any one of the first through fourth features,wherein the first Group III nitride compound semiconductor layer and thesecond Group III nitride compound semiconductor layer have the samecomposition. In the context of the present invention, compositions whichdiffer from one another on doping level (differences of less than 1 mol%) are referred to as the “same composition.”

[0012] The invention drawn to a sixth feature provides a method forfabricating a Group III nitride compound semiconductor substrate asrecited in connection with any one of the first through fifth features,wherein the second Group III nitride compound semiconductor layer andthe third Group III nitride compound semiconductor layer have the samecomposition. In the context of the present invention, compositions whichdiffer from one another on doping level (differences of less than 1 mol%) are referred to as the “same composition.”

[0013] The invention drawn to a seventh feature provides a Group IIInitride compound semiconductor device, which is formed on a Group IIInitride compound semiconductor substrate produced through a method forfabricating a Group III nitride compound semiconductor substrate asrecited in connection with any one of the first through sixth features.

[0014] The invention drawn to an eighth feature provides a Group IIInitride compound semiconductor light-emitting device, which is producedby laminating a different Group III nitride compound semiconductor layeron a Group III nitride compound semiconductor substrate produced througha method for fabricating a Group III nitride compound semiconductorsubstrate as recited in connection with any one of the first throughsixth features.

[0015] The outline of the method for fabricating a Group III nitridecompound semiconductor substrate of the present invention will next bedescribed with reference to FIGS. 1 through 4. Although FIGS. 1 and 3illustrate structures including a substrate base 1 and a buffer layer 2,the buffer layer 2 is not an essential element of the present invention,in view that the object of the present invention is to produce,by-performing etching twice and lateral epitaxial growth twice, a GroupIII nitride compound semiconductor substrate having reduced threadingdislocations in the vertical direction from a first Group III nitridecompound semiconductor layer having threading dislocations in thevertical direction. The gist of the operation and effects of the presentinvention will next be described with reference to embodiments in whicha first Group III nitride compound semiconductor layer 31 havingthreading dislocations in the vertical direction (direction vertical tothe substrate surface) is formed above the substrate base 1 via thebuffer layer 2.

[0016] As shown in FIG. 1(a), the first Group III nitride compoundsemiconductor layer 31 is formed above the substrate base 1 via thebuffer layer 2. Subsequently, as shown in FIG. 1(b), the first Group IIInitride compound semiconductor layer 31 is subjected to etching, so asto form an island-like structure having, for example, a dot, stripe, orgrid shape, thereby providing first trenches/mesas such that depressionsof the substrate base 1 are exposed so as to form the bottoms of thetrenches. Subsequently, a second Group III nitride compoundsemiconductor layer 32 is epitaxially grown, vertically and laterally,with top surfaces of the first mesas or posts and sidewalls of the firsttrenches serving as nuclei for crystal growth, i.e., seeds for crystalgrowth, to thereby fill spaces above the trenches of the substrate base1, while epitaxial growth is effected in the vertical direction. In thiscase, propagation of threading dislocations contained in the first GroupIII nitride compound semiconductor layer 31 can be prevented in theupper portion of the second Group III nitride compound semiconductorlayer 32 that is formed by lateral epitaxial growth (FIGS. 1(c) and1(d)). That is, no threading dislocations propagate, in the verticaldirection, through a portion that is laterally grown with the sidewallsof the trenches serving as nuclei for crystal growth. The first GroupIII nitride compound semiconductor layer 31 is strongly bonded to thesubstrate base 1 via the buffer layer 2. Meanwhile, the second Group IIInitride compound semiconductor layer 32 is not strongly bonded to thesubstrate base 1, since the layer 32 is not in direct contact with thesubstrate base 1, or the area of a portion at which the layer 32 is indirect contact with the substrate base 1 is very small. Therefore,portions of the second Group III nitride compound semiconductor layer 32that are formed above the trenches of the substrate base 1 do notreceive stress directly from the substrate base 1.

[0017] Subsequently, the first mesas (i.e., the first Group III nitridecompound semiconductor layer 31 and the buffer layer 2 that have notundergone etching) are subjected to etching, together with the secondGroup III nitride compound semiconductor layer 32 formed on the layer31. The substrate base 1 is also subjected to etching, to thereby formdepressions or trenches. This etching provides second trenches/mesas;i.e., laterally epitaxially grown portions of the second Group IIInitride compound semiconductor layer 32 (FIG. 2(e)). When, although notillustrated in FIG. 2(e), the first Group III nitride compoundsemiconductor layer 31 is caused to partially remain on the substratebase and to be bonded thereto, the mesas formed of the second Group IIInitride compound semiconductor layer 32 can be provided over a wideregion as shown in FIG. 2(e), in which the mesas can be viewed as ifthey were floating above the substrate base. In this case, threadingdislocations are considerably reduced in the second Group III nitridecompound semiconductor layer 32 which has been formed as the secondmesas. Subsequently, a third Group III nitride compound semiconductorlayer 33 is epitaxially grown, vertically and laterally, with topsurfaces of the second mesas and sidewalls of the second trenchesserving as nuclei for crystal growth, i.e., seeds for crystal growth,which are formed of the second Group III nitride compound semiconductorlayer 32 (FIG. 2(f)). The thus-grown third Group III nitride compoundsemiconductor layer 33 has virtually no threading dislocations thatpropagate therethrough in the vertical direction. Like the case of thesecond Group III nitride compound semiconductor layer 32, the thirdGroup III nitride compound semiconductor layer 33 has virtually nocontact with the substrate base 1. Therefore, portions of the thirdGroup III nitride compound semiconductor layer 33 that are formed abovethe trenches of the substrate base 1 do not receive stress directly fromthe substrate base 1. After the third Group III nitride compoundsemiconductor layer 33 is formed so as to have a large thickness (FIG.2(g)), the substrate base 1 is removed, to thereby produce a Group IIInitride compound semiconductor substrate 30 having virtually nothreading dislocations (FIG. 2(h)). The substrate base 1 is bonded tothe Group III nitride compound semiconductor substrate 30 by means ofmerely a portion including the first Group III nitride compoundsemiconductor layer 31 and the buffer layer 2 that have remained duringformation of the second trenches/mesas, and the area of the portion isvery small. When the portion is removed together with the base substrate1, or when the portion including the first Group III nitride compoundsemiconductor layer 31 and the buffer layer 2 is separated from thesecond and third Group III nitride compound semiconductor layers 32 and33 formed above the trenches of the substrate base 1, the Group IIInitride compound semiconductor substrate 30 having virtually nothreading dislocations can be readily produced. The expression “removingall the underlying layer, excepting a portion thereof” does not excludethe case in which a portion containing threading dislocations is presentto some extent, for the sake of convenience in manufacture. The methodof the present invention encompasses a process in which etching andvertical and lateral epitaxial growth are performed three times or more,and virtually all the underlying layer is removed, to thereby produce aGroup III nitride compound semiconductor substrate; a process in which afourth Group III nitride compound semiconductor layer is formed whilethe third Group III nitride compound semiconductor layer 33 is formed soas to have a large thickness; and a process in which a differentepitaxial technique is employed (the first feature).

[0018] In the aforementioned process, in order to reduce the area of aportion at which the second or third Group III nitride compoundsemiconductor layer is in contact with the substrate base 1, thesubstrate base 1 is subjected to etching to thereby form depressions.Meanwhile, the following process as shown in FIGS. 3 and 4 may beperformed: the surface of a substrate base 1 is exposed; masks 41 and 42are formed on the thus-exposed substrate base 1; and the masks areremoved through wet etching at the final step (i.e., the step subsequentto the step shown in FIG. 4(g)), to thereby provide a space between aGroup III nitride compound semiconductor substrate and the substratebase 1 (the second feature). When the masks are formed of a substancecapable of impeding epitaxial growth of a Group III nitride compoundsemiconductor layer on the masks, during epitaxial growth and afterepitaxial growth, the Group III nitride compound semiconductor layerdoes not receive stress from the substrate base 1 via the masks (thethird feature).

[0019] The aforementioned rapid lateral epitaxial growth can be readilyattained when the sidewalls of the trenches formed by etching of theGroup III nitride compound semiconductor layer 31 are a {11-20} plane(the fourth feature). During lateral epitaxial growth, at least an upperportion of the growth front may remain a {11-20} plane. When the firstGroup III nitride compound semiconductor layer and the second Group IIInitride compound semiconductor layer have the same composition, rapidlateral epitaxial growth can be readily attained (the fifth feature).Similar to the case described above, when the second Group III nitridecompound semiconductor layer and the third Group III nitride compoundsemiconductor layer have the same composition, rapid lateral epitaxialgrowth can be readily attained (the sixth feature).

[0020] Through the procedure described above, the Group III nitridecompound semiconductor substrate 30 can be readily removed from thesubstrate base 1, and threading dislocations contained in the substrate30 can be reduced to the lowest possible level. Although FIGS. 1 through4 illustrate sidewalls of trenches vertical to the substrate base, thepresent invention is not limited thereto, and the sidewalls may beoblique planes. So long as the first Group III nitride compoundsemiconductor layer 31 and the buffer layer 2 are removed through acombination of the first and second trench/mesa formation steps, thetrenches formed in the first or second trench/mesa formation step mayhave V-shaped cross sections. These features are equally applied to thedescriptions below.

[0021] When a device is formed on the Group III nitride compoundsemiconductor substrate produced through the above process, asemiconductor device having a layer containing few defects and endowedwith high mobility can be provided (the seventh feature).

[0022] When a light-emitting device is formed on the Group III nitridecompound semiconductor substrate produced through the above process, alight-emitting device endowed with improved life time and an improved LDthreshold value can be provided (the eighth feature).

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a series of cross-sectional views showing the first halfof the steps of fabricating a Group III nitride compound semiconductorsubstrate according to a first embodiment of the present invention.

[0024]FIG. 2 is a series of cross-sectional views showing the secondhalf of the steps of fabricating a Group III nitride compoundsemiconductor substrate according to the first embodiment of the presentinvention.

[0025]FIG. 3 is a series of cross-sectional views showing the first halfof the steps of fabricating a Group III nitride compound semiconductorsubstrate according to a second embodiment of the present invention.

[0026]FIG. 4 is a series of cross-sectional views showing the secondhalf of the steps of fabricating a Group III nitride compoundsemiconductor substrate according to the second embodiment of thepresent invention.

[0027]FIG. 5 is a schematic representation showing an example of etchingof first and second Group III nitride compound semiconductor layers, andthe second and third Group III nitride compound semiconductor layerswhich have been formed.

[0028]FIG. 6 is a cross-sectional view showing the structure of a GroupIII nitride compound semiconductor light-emitting device according to athird embodiment of the present invention.

[0029]FIG. 7 is a cross-sectional view showing the structure of a GroupIII nitride compound semiconductor light-emitting device according to afourth embodiment of the present invention.

[0030]FIG. 8 is a schematic representation showing another example ofetching of the first Group III nitride compound semiconductor layer.

[0031]FIG. 9 is a cross-sectional view showing threading dislocationspropagating in a Group III nitride compound semiconductor.

BEST MODE FOR CARRYING OUT THE INVENTION

[0032]FIGS. 1 through 4 schematically show a mode for carrying out themethod for fabricating a Group III nitride compound semiconductorsubstrate of the present invention. A substrate base 1, a buffer layer2, and a first Group III nitride compound semiconductor layer 31 areformed (FIG. 1(a)), and the layers 2 and 31 are subjected to etching, tothereby form trenches (FIG. 1(b)). As a result of etching, first mesasand trenches are formed, the unetched surfaces of the layer 31 becomethe top surfaces of the mesas, sidewalls of the trenches are formed, andbottoms of the trenches are formed; i.e., depressions are formed on thesubstrate base 1. The sidewalls are, for example, {11-20} planes.Subsequently, under conditions of lateral epitaxial growth, a secondGroup III nitride compound semiconductor layer 32 is epitaxially grownwith the sidewalls of the first trenches and the top surfaces of thefirst mesas serving as nuclei for crystal growth, i.e., seeds forcrystal growth. A metal-organic growth process enables easy lateralepitaxial growth while the growth fronts remain the {11-20} planes.Portions of the second Group III nitride compound semiconductor layer 32that are laterally grown from the sidewalls of the trenches are freefrom propagation of threading dislocations (FIG. 1(c)). The form ofetching and lateral epitaxial growth conditions are determined such thatthe fronts of lateral growth extending from the opposite sidewalls ofthe trenches fill the etched trenches, whereby threading dislocationsare suppressed in the regions of the second Group III nitride compoundsemiconductor layer 32 formed above the bottoms of the etched trenches(FIG. 1(d)). Thereafter, the first Group III nitride compoundsemiconductor layer 31 and the buffer layer 2 are removed by etching,together with the second Group III nitride compound semiconductor layer32 formed on the layer 31, and the surface of the substrate base 1, tothereby provide second trenches/mesas formed of the second Group IIInitride compound semiconductor layer 32 with suppressed threadingdislocations (FIG. 2(e)). When, although not illustrated in FIG. 2(e),the first Group III nitride compound semiconductor layer 31 is caused topartially remain on the substrate base and to be bonded thereto, themesas formed of the second Group III nitride compound semiconductorlayer 32 can be provided over a wide region as shown in FIG. 2(e), inwhich the mesas can be viewed as if they were floating above thesubstrate base. Subsequently, a third Group III nitride compoundsemiconductor layer 33 is epitaxially grown, vertically and laterally,with top surfaces of the second mesas and sidewalls of the secondtrenches serving as nuclei for crystal growth, i.e., seeds for crystalgrowth, the mesas and trenches being formed of the second Group IIInitride compound semiconductor layer 32 with suppressed threadingdislocations (FIG. 2(f)), whereby virtually no threading dislocationsare generated in the third Group III nitride compound semiconductorlayer 33. After the third Group III nitride compound semiconductor layer33 is formed so as to have a large thickness (FIG. 2(g)), the substratebase 1 is removed, to thereby produce a Group III nitride compoundsemiconductor substrate 30 (FIG. 2(h)). The substrate base 1 is bondedto the Group III nitride compound semiconductor substrate 30 via merelya portion including the first Group III nitride compound semiconductorlayer 31 and the buffer layer 2 that have remained during formation ofthe second trenches/mesas. Therefore, when the portion is removed, orwhen the portion is separated from the second and third Group IIInitride compound semiconductor layers 32 and 33, the Group III nitridecompound semiconductor substrate 30 is produced. As shown in FIGS. 3 and4, when masks 41 on which a Group III nitride compound semiconductorlayer is not epitaxially grown are provided at the bottoms of the firsttrenches, and masks 42 on which a Group III nitride compoundsemiconductor layer is not epitaxially grown are provided at the bottomsof the second trenches, in a manner similar to that described above, theGroup III nitride compound semiconductor substrate 30 can be readilyproduced. The masks 41 and 42 are preferably formed of a substance whichcan be removed through, for example, wet etching.

[0033] There may be employed an underlying layer including a pluralityof sub-layer units, each unit having a buffer layer and a Group IIInitride compound semiconductor layer grown epitaxially on the bufferlayer, wherein the lowermost unit includes a buffer layer formeddirectly on the substrate base 1. Regardless of the number of the units,the substrate base 1 is exposed through the bottoms of the trenchesformed in the underlying layer. Portions of the Group III nitridecompound semiconductor layer 32 formed above the bottoms of the trenchesare formed primarily through lateral epitaxial growth while the GroupIII nitride compound semiconductor layer 31, which is the top layer ofthe mesas, serves as nuclei, thereby becoming regions in which threadingdislocations of vertical propagation are suppressed.

[0034] The aforementioned modes for carrying out the invention mayemploy any of the following processes.

[0035] When Group III nitride compound semiconductor layers aresuccessively formed on a substrate base, the substrate base may beformed from an inorganic crystal compound such as sapphire, silicon(Si), silicon carbide (SiC), spinel (MgAl₂O₄), ZnO, or MgO; a GroupIII-V compound semiconductor such as gallium phosphide or galliumarsenide; or a Group III nitride compound semiconductor having threadingdislocations, such as gallium nitride (GaN).

[0036] A preferred process for forming a Group III nitride compoundsemiconductor layer is metal-organic chemical vapor deposition (MOCVD)or metal-organic vapor phase epitaxy (MOVPE). However, molecular beamepitaxy (MBE), halide vapor phase epitaxy (Halide VPE), liquid phaseepitaxy (LPE), or the like may be used. Also, individual layers may beformed by different growth processes.

[0037] When a Group III nitride compound semiconductor layer is to beformed on, for example, a sapphire substrate serving as a substratebase, in order to impart good crystallinity to the layer, a buffer layeris preferably formed for the purpose of correcting lattice mismatch withthe sapphire substrate. When a substrate of another material is to beused as a substrate base, employment of a buffer layer is alsopreferred. A buffer layer is preferably of a Group III nitride compoundsemiconductor Al_(x)Ga_(y)In_(1−x−y)N formed at low temperature (0≦x≦1,0≦y≦1, 0≦x+y≦1), more preferably of Al_(x)Ga_(1−x)N (0≦x≦1). This bufferlayer may be a single layer or a multi-component layer containing layersof different compositions. A buffer layer may be formed at a lowtemperature of 380 to 420° C. or by MOCVD at a temperature of 1,000 to1,180° C. Alternatively, an AlN buffer layer can be formed by a reactivesputtering process using a DC magnetron sputtering apparatus and, asmaterials, high-purity aluminum and nitrogen gas. Similarly, a bufferlayer represented by the formula Al_(x)Ga_(y)In_(1−x−y)N (0≦x≦1, 0≦y≦1,0≦x+y≦1, arbitrary composition) can be formed. Furthermore, vapordeposition, ion plating, laser abrasion, or ECR can be employed. When abuffer layer is to be formed by physical vapor deposition, physicalvapor deposition is performed preferably at 200 to 600° C., morepreferably 300 to 500° C., most preferably 350 to 450° C. When physicalvapor deposition, such as sputtering, is employed, the thickness of abuffer layer is preferably 100 to 3,000 Å, more preferably 100 to 400 Å,most preferably 100 to 300 Å. A multi-component layer may contain, forexample, alternating Al_(x)Ga_(1−x)N (0≦x≦1) layers and GaN layers.Alternatively, a multi-component layer may contain alternating layers ofthe same composition formed at a temperature of not higher than 600° C.and at a temperature of not lower than 1,000° C. Of course, thesearrangements may be combined. Also, a multi-component layer may containthree or more different types of Group III nitride compoundsemiconductors Al_(x)Ga_(y)In_(1−x−y)N (0≦x≦1, 0≦y≦1, 0≦x+y≦1).Generally, a buffer layer is amorphous and an intermediate layer ismonocrystalline. Repetitions of unit of a buffer layer and anintermediate layer may be formed, and the number of repetitions is notparticularly limited. The greater the number of repetitions, the greaterthe improvement in crystallinity.

[0038] The present invention is substantially applicable even when thecomposition of a buffer layer and that of a Group III nitride compoundsemiconductor formed on the buffer layer are such that a portion ofGroup III elements are replaced with boron (B) or thallium (Tl) or aportion of nitrogen (N) atoms are replaced with phosphorus (P), arsenic(As), antimony (Sb), or bismuth (Bi). Also, the buffer layer and theGroup III nitride compound semiconductor may be doped with any one ofthese elements to such an extent as not to appear in the compositionthereof. For example, a Group III nitride compound semiconductor whichis represented by Al_(x)Ga_(1−x)N (0≦x≦1) and which does not containindium (In) and arsenic (As) may be doped with indium (In), which islarger in atomic radius than aluminum (Al) and gallium (Ga), or arsenic(As), which is larger in atomic radius than nitrogen (N), to therebyimprove crystallinity through compensation, by means of compressionstrain, for crystalline expansion strain induced by dropping off ofnitrogen atoms. In this case, since acceptor impurities easily occupythe positions of Group III atoms, p-type crystals can be obtained asgrown. Through the thus-attained improvement of crystallinity combinedwith the features of the present invention, threading dislocation can befurther reduced to approximately {fraction (1/100)} to {fraction(1/1,000)}. In the case of an underlying layer containing two or morerepetitions of a buffer layer and a Group III nitride compoundsemiconductor layer, the Group III nitride compound semiconductor layersare further preferably doped with an element greater in atomic radiusthan a predominant component element. When a light-emitting element isproduced after formation of a Group III nitride compound semiconductorsubstrate, use of a binary or ternary Group III nitride compoundsemiconductor is preferred.

[0039] When an n-type Group III nitride compound semiconductor layer isto be formed, a Group IV or Group VI element, such as Si, Ge, Se, Te, orC, can be added as an n-type impurity. A Group II or Group IV element,such as Zn, Mg, Be, Ca, Sr, or Ba, can be added as a p-type impurity.The same layer may be doped with a plurality of n-type or p-typeimpurities or doped with both n-type and p-type impurities. Thus, ann-type or p-type Group III nitride compound semiconductor substratehaving arbitrary conductivity can be produced.

[0040] Lateral epitaxial growth preferably progresses such that thefront of lateral epitaxial growth is perpendicular to a substrate base.However, lateral epitaxial growth may progress while slant facets withrespect to the substrate base are maintained. In this case, trenches mayhave a V-shaped cross section.

[0041] Preferably, lateral epitaxial growth progresses such that atleast an upper portion of the front of lateral epitaxial growth isperpendicular to the surface of a substrate base. More preferably,growth fronts are {11-20} planes of a Group III nitride compoundsemiconductor layer.

[0042] The depth and width of trenches to be etched are appropriatelydetermined such that lateral epitaxial growth fills the trenches.

[0043] When the crystal orientation of a Group III nitride compoundsemiconductor layer to be formed on a substrate base can be predicted,masking or etching in the form of stripes perpendicular to the a-plane({11-20} plane) or the m-plane ({1-100} plane) of the Group III nitridecompound semiconductor layer is favorable. The aforementioned stripe ormask patterns may be island-like or grid-like or may assume other forms.The front of lateral epitaxial growth may be perpendicular or oblique tothe surface of a substrate base. In order for the a-plane; i.e., the(11-20) plane, of a Group III nitride compound semiconductor layer tobecome the front of lateral epitaxial growth, the lateral direction ofstripes must, for example, be perpendicular to the m-plane; i.e., the(1-100) plane, of the Group III nitride compound semiconductor layer.For example, when the surface of a substrate base is the a-plane or thec-plane of sapphire, the m-plane of sapphire usually matches the a-planeof a Group III nitride compound semiconductor layer formed on thesubstrate base. Thus, etching is performed according to the arrangementof the planes. In the case of dot-like, grid-like, or island-likeetching, planes that define an outline (sidewalls) are preferably{11-20} planes.

[0044] An etching mask may be formed of a multi-layer film formed from apolycrystalline semiconductor such as polycrystalline silicon or apolycrystalline nitride semiconductor; an oxide or a nitride, such assilicon oxide (SiO_(x)), silicon nitride (SiN_(x)), titanium oxide(TiO_(x)), or zirconium oxide (ZrO_(x)); or a metal of high meltingpoint, such as titanium (Ti) or tungsten (W). The film may be formedthrough any known method, such as a vapor-growth method (e.g.,deposition, sputtering, or CVD). The mask may be removed during lateralepitaxial growth, or a Group III nitride compound semiconductor layermay be laterally epitaxially grown so as to cover the mask withoutremoval of the mask. When the mask is removed, the laterally epitaxiallygrown Group III nitride compound semiconductor layer exhibits improvedcrystallinity. Meanwhile, when the mask is caused to remain,dislocations may be generated at the edge of the mask.

[0045] Reactive ion etching (RIE) is preferred, but any other etchingprocess may be employed. When trenches having sidewalls oblique to thesurface of a substrate base are to be formed, anisotropic etching isemployed. By means of anisotropic etching, trenches are formed such thatthe trenches have a V-shaped cross section.

[0046] No particular limitation is imposed on the mask provided at thebottoms of trenches, so long as the mask can be removed through wetetching. Therefore, the aforementioned etching mask may be employed. Themask provided at the bottoms of the trenches may be removed through anywet etching technique. When the mask provided at the bottoms of thetrenches is formed of silicon dioxide, the mask may be removed throughwet etching employing a hydrofluoric-acid-based etchant.

[0047] A semiconductor device, such as an FET or a light-emittingdevice, can be formed on the aforementioned Group III nitride compoundsemiconductor substrate having virtually no threading dislocations. Inthe case where a light-emitting device is formed, a light-emitting layermay have a multi-quantum well (MQW) structure, a single-quantum well(SQW) structure, a homo-structure, a single-hetero-structure, or adouble-hetero-structure, or the layer may be formed by means of, forexample, a pin junction or a pn junction.

[0048] In order to separate the aforementioned Group III nitridecompound semiconductor substrate having virtually no threadingdislocations from the substrate base 1, any known technique, such asmechanochemical polishing, may be employed. The Group III nitridecompound semiconductor substrate produced through the method of thepresent invention may be employed for forming a larger Group III nitridecompound semiconductor crystal.

[0049] Embodiments of the present invention in which light-emittingelements are produced will next be described. The present invention isnot limited to the embodiments described below. The present inventiondiscloses a method for fabricating a Group III nitride compoundsemiconductor substrate applicable to fabrication of any device.

[0050] The Group III nitride compound semiconductor of the presentinvention was produced through metal-organic vapor phase epitaxy(hereinafter called “MOVPE”). The following gasses were employed:ammonia (NH₃), carrier gas (H₂ or N₂), trimethylgallium (Ga(CH₃)₃,hereinafter called “TMG”)), trimethylaluminum (Al(CH₃)₃, hereinaftercalled “TMA”), trimethylindium (In(CH₃)₃, hereinafter called “TMI”), andcyclopentadienylmagnesium (Mg(C₅H₅)₂, hereinafter called “Cp₂Mg”).

[0051] [First Embodiment]

[0052]FIGS. 1 and 2 show the steps of the present embodiment. Amonocrystalline sapphire substrate 1 whose principle surface for crystalgrowth is an a-plane was cleaned by organic cleaning and heat treatment.The temperature of the substrate 1 was lowered to 400° C., and H₂ (10L/min), NH₃ (5 L/min), and TMA (20 μmol/min) were fed for about threeminutes, to thereby form an AlN buffer layer 2 (thickness: about 40 nm)on the substrate 1. Subsequently, while the temperature of the sapphiresubstrate 1 was maintained at 1,000° C., H₂ (20 L/min), NH₃ (10 L/min),and TMG (300 μmol/min) were introduced, to thereby form a GaN layer 31(thickness: about 1 μm) (FIG. 1(a)).

[0053] By use of a hard bake resist mask, stripe-shaped trenches eachhaving a width of 10 μm and a depth of about 1.2 μm were formed atintervals of 10 μm through selective dry etching employing reactive ionetching (RIE). As a result, mesas formed of the GaN layer 31 and thebuffer layer 2 each having a width of 10 μm and a height of about 1 μm,and depressions of the sapphire substrate 1 each having a depth of 0.2μm were alternately formed (FIG. 1(b)). At this time, the {11-20} planesof the GaN layer 31 were caused to serve as the sidewalls of thetrenches of a depth of 1 μm.

[0054] Subsequently, while the temperature of the sapphire substrate 1was maintained at 1,150° C., H₂ (20 L/min), NH₃ (10 L/min), and TMG (2μmol/min) were introduced, to thereby form a GaN layer 32 by lateralepitaxial growth performed while the sidewalls of the trenches of adepth of 1 μm; i.e., the {11-20} planes of the GaN layer 31, served asnuclei for crystal growth. At an initial stage, vertical epitaxialgrowth from the top surfaces of the mesas or posts was suppressed (FIG.1 (c)). Lateral epitaxial growth was performed while the {11-20} planesprimarily served as the growth fronts, whereby the trenches were filled,and the surface of the GaN layer 32 became flat. The overall thicknessof the GaN layer 31 and the GaN layer 32 was found to be about 1.5 μm(FIG. 1(d)).

[0055] Subsequently, by use of a hard bake resist mask, stripe-shapedtrenches each having a width of 10 μm and a depth of about 1.7 μm wereformed at intervals of 10 μm through selective dry etching employingreactive ion etching (RIE), whereby virtually all the GaN layer 31 andthe buffer layer 2 was removed, together with the GaN layer 32 formedatop the GaN layer 31 and the surface of the sapphire substrate 1 (FIG.2(e)). FIG. 5 schematically shows the thus-formed structure.Specifically, FIG. 5(a) is a plan view corresponding to FIG. 1(b), andreference letter B of FIG. 5(a) denotes the depressions or trenchesformed in the sapphire substrate 1. FIG. 5(b) is a plan viewcorresponding to FIG. 2(e), and reference letter A of FIG. 5(b) denotesthe exposed depressions or trenches of the sapphire substrate 1. Asshown in FIG. 5(b) (not illustrated in FIG. 2(e)), the GaN layer 31 iscaused to remain on the periphery of the sapphire substrate 1.

[0056] Through the aforementioned etching, mesas formed of the GaN layer32 each having a width of 10 pn and a height of about 1.5 μm, andtrenches of the sapphire substrate 1 each having a width of 10 μm and adepth of 0.2 μm were alternately formed (FIG. 2(e)). At this time, the{11-20} planes of the GaN layer 32 were served as the sidewalls of thetrenches of a depth of 1.5 μm.

[0057] Subsequently, while the temperature of the sapphire substrate 1was maintained at 1,150° C., H₂ (20 L/min), NH₃ (10 L/min), and TMG (2μmol/min) were introduced, to thereby form a GaN layer 33 throughlateral epitaxial growth performed while the sidewalls of the trenchesof a depth of 1.5 μm; i.e., the {11-20} planes of the GaN layer 32,served as nuclei for crystal growth. At an initial stage, verticalepitaxial growth from the top surfaces of the mesas was suppressed (FIG.2(f)). Lateral epitaxial growth was performed while the {11-20} planesprimarily served as the growth fronts, whereby the trenches were filled,and the surface of the GaN layer 33 became flat. Thereafter, H₂ (20L/min), NH₃ (10 L/min), and TMG (300 μmol/min) were introduced, tothereby further grow the GaN layer 33 until the overall thickness of theGaN layer 32 and the GaN layer 33 became 300 μm (FIG. 2(g)). Thereafter,a GaN substrate 30 including the GaN layer 32 and the GaN layer 33 wasseparated, through dicing, from the sapphire substrate 1 and theremaining portion of the GaN layer 31 (see FIG. 5(c)) at the boundarybetween the GaN substrate 30 and the remaining portion of the GaN layer31 (FIG. 2(h)). The thus-produced GaN substrate 30 was found to containvirtually no threading dislocations.

[0058] [Second Embodiment]

[0059]FIGS. 3 and 4 show the steps of the present embodiment. Amonocrystalline sapphire substrate 1 whose principal surface an a-planewas cleaned through organic cleaning and heat treatment. The temperatureof the substrate 1 was lowered to 400° C., and H₂ (10 L/min), NH₃ (5L/min), and TMA (20 μmol/min) were fed for about three minutes, tothereby form an AlN buffer layer 2 (thickness: about 40 nm) on thesubstrate 1. Subsequently, while the temperature of the sapphiresubstrate 1 was maintained at 1,000° C., H₂ (20 L/min), NH₃ (10 L/min),and TMG (300 μmol/min) were introduced, to thereby form a GaN layer 31(thickness: about 1 μm).

[0060] By use of a hard bake resist mask, stripe-shaped trenches eachhaving a width of 10 μm and a depth of about 1 μm were formed atintervals of 10 μm through selective dry etching employing reactive ionetching (RIE). As a result, mesas formed of the GaN layer 31 and thebuffer layer 2 each having a width of 10 μm and a height of about 1 μm,and trenches each having a width of 10 μm and having the sapphiresubstrate 1 exposed at the bottom thereof were alternately formed (FIG.3(a)). At this time, the {11-20} planes of the GaN layer 31 were servedas the sidewalls of the trenches of a depth of 1 μm.

[0061] Subsequently, a silicon dioxide (SiO₂) film was uniformly formedthrough sputtering. Thereafter, a resist was applied onto the SiO₂ film;a portion of the resist that covered a necessary portion of the silicondioxide film was remained through photolithography; and a portion of thesilicon dioxide film that was not covered with the resist was subjectedto wet etching, to thereby form a wafer having the structure shown inFIG. 3(b) and including masks 41.

[0062] Subsequently, while the temperature of the sapphire substrate 1was maintained at 1,150° C, H₂ (20 L/min), NH₃ (10 L/min), and TMG (2μmol/min) were introduced, to thereby form a GaN layer 32 throughlateral epitaxial growth performed while the sidewalls of the trenchesof a depth of 1 μm; i.e., the {11-20} planes of the GaN layer 31, servedas nuclei for crystal growth. At an initial stage, vertical epitaxialgrowth from the top surfaces of the mesas was suppressed (FIG. 3(c)).Lateral epitaxial growth was performed while the {11-20} planesprimarily served as the growth fronts, whereby the trenches were filled,and the surface of the GaN layer 32 became flat. The overall thicknessof the GaN layer 31 and the GaN layer 32 was found to be about 1.5 μm(FIG. 3(d)).

[0063] Subsequently, by use of a hard bake resist mask, stripe-shapedtrenches each having a width of 10 μm and a depth of about 1.5 μm wereformed at intervals of 10 μm through selective dry etching employingreactive ion etching (RIE), whereby virtually the entirety of the GaNlayer 31 and the buffer layer 2 were removed, together with the GaNlayer 32 formed on the GaN layer 31. As a result, mesas formed of theGaN layer 32 each having a width of 10 μm and a height of about 1.5 μm,and trenches each having a width of 10 μm and having the sapphiresubstrate 1 exposed at the bottom thereof were alternately formed. Atthis time, the {11-20? planes of the GaN layer 32 were served as thesidewalls of the trenches of a depth of 1.5 μm. Subsequently, a silicondioxide (SiO₂) film was uniformly formed through sputtering. Thereafter,a resist was applied onto the SiO₂ film; a portion of the resist thatcovered a necessary portion of the silicon dioxide film was caused toremain through photolithography; and a portion of the silicon dioxidefilm that was not covered with the resist was subjected to wet etching,to thereby form a wafer including SiO₂ masks 42 (FIG. 4 (e)). Theaforementioned procedure of the second embodiment is similar to that ofthe first embodiment, and the thus-formed structure is schematicallyshown in FIG. 5. Specifically, FIG. 5(a) is a plan view corresponding toFIG. 3(b), and reference letter B of FIG. 5(a) denotes the SiO₂ masks 41formed on the sapphire substrate 1. FIG. 5(b) is a plan viewcorresponding to FIG. 4(e), and reference letter A of FIG. 5(b) denotesthe exposed SiO₂ masks 42 formed on the sapphire substrate 1. As shownin FIG. 5(b) (not illustrated in FIG. 4(e)), in consideration ofworkability, the GaN layer 31 is caused to remain on the periphery ofthe sapphire substrate 1.

[0064] Subsequently, while the temperature of the sapphire substrate 1was maintained at 1,150° C., H₂ (20 L/min), NH₃ (10 L/min), and TMG (2μmol/min) were introduced, to thereby form a GaN layer 33 throughlateral epitaxial growth performed while the sidewalls of the trenchesof a depth of 1.5 μm; i.e., the {11-20} planes of the GaN layer 32,served as nuclei for crystal growth. At an initial stage, verticalepitaxial growth from the top surfaces of the mesas was suppressed (FIG.4(f)). Lateral epitaxial growth was performed while the {11-20} planesprimarily served as the growth fronts, whereby the trenches were filled,and the surface of the GaN layer 33 became flat. Thereafter, H₂ (20L/min), NH₃ (10 L/min), and TMG (300 μmol/min) were introduced, tothereby further grow the GaN layer 33 until the overall thickness of theGaN layer 32 and the GaN layer 33 became 300 μm (FIG. 4(g)).Subsequently, the SiO₂ masks 41 and 42 were removed through wet etchingemploying a hydrofluoric-acid-based etchant. Thereafter, a GaN substrate30 including the GaN layer 32 and the GaN layer 33 was separated,through dicing, from the sapphire substrate 1 and the remaining portionof the GaN layer 31 (see FIG. 5(c)) at the boundary between the GaNsubstrate 30 and the remaining portion of the GaN layer 31 (FIG. 4(h)).The thus-produced GaN substrate 30 was found to contain virtually nothreading dislocations.

[0065] [Third Embodiment]

[0066] In the present embodiment, the first embodiment was modified suchthat silane (SiH₄) was fed during formation of the GaN layers 32 and 33,to thereby produce an n-type GaN substrate 101, and the thus-producedsubstrate 101 was employed. On the n-type GaN substrate 101, a silicon(Si)doped n-Al_(0.15)Ga_(0.85)N layer 102 (thickness: 2 μm) was formedat a temperature of 1,150° C. through feeding of H₂ (10 L/min), NH₃ (10L/min), TMG (100 mol/min), TMA (10 μmol/min), and silane (SiH₄) dilutedwith H₂ gas to 0.86 ppm (0.2 μmol/min). On the n-Al_(0.15)Ga_(0.85)Nlayer 102, a silicon (Si)-doped GaN n-guide layer 103, an MQW-structuredlight-emitting layer 104, a magnesium (Mg)-doped GaN p-guide layer 105,a magnesium (Mg)-doped Al_(0.08Ga) _(0.92)N p-cladding layer 106, and amagnesium (Mg)-doped GaN p-contact layer 107 were formed. Subsequently,an electrode 108A of gold (Au) was formed on the p-contact layer 107,and an electrode 108B of aluminum (Al) was formed on the back side ofthe n-type GaN substrate 101 (FIG. 6). A laser diode (LD) 100 was formedon the n-type GaN substrate 101 containing virtually no threadingdislocations. The thus-formed laser diode (LD) 100 exhibited significantimprovement of life time and light-emitting efficiency.

[0067] [Fourth Embodiment]

[0068] In the present embodiment, an n-type GaN substrate was employed.On an n-type GaN substrate 201, an n-Al_(0.15)Ga_(0.85)N layer 202, alight-emitting layer 203, and a magnesium (Mg)-doped Al_(0.15)Ga_(0.85)Np-cladding layer 204 were formed. Subsequently, an electrode 205A ofgold (Au) was formed on the p-cladding layer 204, and an electrode 205Bof aluminum (Al) was formed on-the back side of the GaN substrate 201(FIG. 7). The thus-formed light-emitting diode (LED) 200 exhibitedsignificant improvement of life time and light-emitting efficiency.

[0069] [Modification of Etching]

[0070]FIG. 8 shows an example in which island-like mesas are formed bymeans of three groups of {11-20} planes. To facilitate understanding,the schematic view of FIG. 8(a) includes a peripheral region formed bymeans of three groups of {11-20} planes. In actuality, tens of millionsof island-like mesas may be formed per wafer. In FIG. 8(a), the area ofthe bottoms of the trenches B is three times the area of the topsurfaces of the island-like mesas. In FIG. 8(b), the area of the bottomsof the trenches B is eight times the area of the top surfaces of theisland-like mesas.

1. A method for fabricating a Group III nitride compound semiconductor substrate through epitaxial growth of a Group III nitride compound semiconductor layer on a substrate base, and removal of the substrate base, which method comprises a step of forming an underlying layer on a substrate base, the underlying layer comprising at least one Group III nitride compound semiconductor layer, and the uppermost layer of the underlying layer being a first Group III nitride compound semiconductor layer; a first trench/mesa formation step in which at least a portion of the underlying layer and at least a portion of the surface of the substrate base are removed through etching so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas formed on the underlying layer and trenches whose bottoms sink into the surface of the substrate base; a first lateral epitaxial growth step in which a second Group III nitride compound semiconductor layer is epitaxially grown, vertically and laterally, with top surfaces of the mesas and sidewalls of the trenches serving as nuclei for crystal growth, the mesas and trenches being formed by etching of the first Group III nitride compound semiconductor layer so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby filling upper portions of the trenches and covering the mesas; a second trench/mesa formation step in which the entire underlying layer that has not undergone etching in the first trench/mesa formation step, excepting a portion of the underlying layer, is removed by etching, together with the second Group III nitride compound semiconductor layer formed on the underlying layer, and at least a portion of the surface of the substrate base, so as to provide a trench/mesa structure including mesas formed on the remaining second Group III nitride compound semiconductor layer and trenches whose bottoms sink into the surface of the substrate base; a second lateral epitaxial growth step in which a third Group III nitride compound semiconductor layer is epitaxially grown, vertically and laterally, with top surfaces of the mesas and sidewalls of the trenches serving as nuclei for crystal growth, the mesas and trenches being formed through etching of the second Group III nitride compound semiconductor layer, thereby filling upper portions of the trenches and covering the mesas; and a step of removing the substrate base and the underlying layer which has not been removed in the second trench/mesa formation step, to thereby produce a substrate comprising the second and third Group III nitride compound semiconductor layers.
 2. A method for fabricating a Group III nitride compound semiconductor substrate comprising epitaxial growth of a Group III nitride compound semiconductor layer on a substrate base, and removal of the substrate base, which method comprises a step of forming an underlying layer on a substrate base, the underlying layer comprising at least one Group III nitride compound semiconductor layer, and the uppermost layer of the underlying layer being a first Group III nitride compound semiconductor layer; a first trench/mesa formation step in which the underlying layer is etched so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure, such that the substrate base is exposed so as to provide the bottoms of trenches; a first mask formation step in which first masks are formed at the bottoms of the trenches formed in the first trench/mesa formation step, such that the upper surfaces of the first masks are positioned below the top surface of the uppermost layer of the underlying layer; a first lateral epitaxial growth step in which a second Group III nitride compound semiconductor layer is epitaxially grown, vertically and laterally, with top surfaces of mesas and sidewalls of the trenches serving as nuclei for crystal growth, the mesas and trenches being formed by etching of the first Group III nitride compound semiconductor layer so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby filling spaces above the first masks and covering the mesas; a second trench/mesa formation step in which substantially the entire underlying layer that has not undergone etching in the first trench/mesa formation step is removed by etching, together with the second Group III nitride compound semiconductor layer formed on the underlying layer, so as to provide a trench/mesa structure including mesas formed on the remaining second Group III nitride compound semiconductor layer and trenches such that the substrate base is exposed so as to provide the bottoms of the trenches; a second mask formation step in which second masks are formed at the bottoms of the trenches formed in the second trench/mesa formation step, such that the upper surfaces of the second masks are positioned below the top surface of the second Group III nitride compound semiconductor layer; a second lateral epitaxial growth step in which a third Group III nitride compound semiconductor layer is epitaxially grown, vertically and laterally, with top surfaces of the mesas and sidewalls of the trenches serving as nuclei for crystal growth, the mesas and trenches being formed by etching of the second Group III nitride compound semiconductor layer, thereby filling spaces above the second masks and covering the mesas; a step of removing the first and second masks by wet etching; and a step of removing the substrate base, to thereby produce a substrate comprising the second and third Group III nitride compound semiconductor layers.
 3. A method for fabricating a Group III nitride compound semiconductor substrate according to claim 2, wherein the masks are formed of a substance capable of impeding epitaxial growth of a Group III nitride compound semiconductor layer on the masks.
 4. A method for fabricating a Group III nitride compound semiconductor substrate according to any one of claims 1 through 3, wherein virtually all the sidewalls of the trenches formed in the first and second trench/mesa formation steps are a [11-20} plane.
 5. A method for fabricating a Group III nitride compound semiconductor substrate according to any one of claims 1 through 4, wherein the first Group III nitride compound semiconductor layer and the second Group III nitride compound semiconductor layer have the same composition.
 6. A method for fabricating a Group III nitride compound semiconductor substrate according to any one of claims 1 through 5, wherein the second Group III nitride compound semiconductor layer and the third Group III nitride compound semiconductor layer have the same composition.
 7. A Group III nitride compound semiconductor device, which is formed on a Group III nitride compound semiconductor substrate produced through a method for fabricating a Group III nitride compound semiconductor substrate as recited in any one of claims 1 through
 6. 8. A Group III nitride compound semiconductor light-emitting device, which is produced by laminating a different Group III nitride compound semiconductor layer on a Group III nitride compound semiconductor substrate produced by a method for fabricating a Group III nitride compound semiconductor substrate as recited in any one of claims 1 through
 6. 